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p.3 #19 · Foveon - Sensor size - megapixels. | |
Daniel Heineck wrote:
I need to back off my statement of "Foveon being dumb" a bit, but I do stand behind it being a fabrication nightmare -- specifically isolating the different photodiodes from electron diffusion.
I agree -- but also, building sensors in multiple layers is another nightmare, simply because every layer requires another pass through the process, which adds to cost... and combine that with the fact that the Foveon has its read circuitry on the back of the chip on the edges like most other sensors, and now suddenly you need MORE layers...
I only responded that way to the statement of Foveon being dumb because it's equivalent to saying we shouldn't bother climbing Mount Rainier, because it's hard.
Another problem is the sensitivity of the sensor to incident light angle. I'm also wondering how much real estate they're losing to transistors--it seems more than an equivalent bayer design given their noise problems. Does Foveon X3 use microlenses to regain some of their real estate back and possibly improve the angle of incidence?
I don't know for sure, but I'd expect so; being clever doesn't get them out of dealing with the same physics as everyone else 
The Intels of the world have the $$$ and the vision to be able to beat their heads into the ground for several decades to get a superior technology working.
They do now, but Intel started off as a puny little upstart with a crappy chip. Intel wasn't a particularly large company as far as semiconductor manufacturers go when they started using bicMOS manufacturing. And AMD isn't exactly flush with cash, yet they're actually implementing immersion lithogrphy, which no one else had been able to do in a high-volume fab...
Even then they screw up plenty. Think about how long and how much it took them to get HfO2 to work. Foveon and Sigma don't have that money nor momentum and are working with a foundry (Nat'l Semiconductor), which isn't going to spend the money to get it to work well either. Foveon needs a dedicated fab and a LOT of process development to really demonstrate its a better technology.
That's probably why Sigma made the DP-1 and bought Foveon; if Sigma can make enough sales volume with point and shoot cameras using Foveon sensors, they can start making some gains from economies of scale. That's obviously a big if and still no guarantee, of course.
Best thing that could happen to Foveon is someone big decides its worth going for and buys them out. For a small company to make it in semi fab, they either need to have their IP purchased by someone who can actually make it a reality or invent something ridiculously simple, but conceptually brilliant. I just don't see Foveon in either of those two camps.
Well, the buying out part happened... let's see what happens next.
Canon, Nikon (Sony), ...etc aren't exactly building barn burner chips either. The design behind these chips is pretty simple and "relatively" easy to design. There aren't too many mask steps if I've done my research correctly. The biggest challenge they've got is getting high yields on absolutely enormous chips.
AFAIK that's true. The big chips are expensive because they're big, and Intel isn't making them 
I think also that they're less tolerant of errors than most other chips, since most chips, including the massive current x86 monstrosities, are mostly cache... bad cache blocks aren't a problem because the designers can plan for that and build in redundancy, but how would you do that for a bad photosite? You can't just route the data from another one.
Anyhow, if anyone wants to talk more about this stuff, shoot me a PM. I'm a big nerd when it comes to fabrication and would love to talk shop.
Yeah, I guess this should probably be the last public post on the subject, unless others are interested 
Not that I'm opposed to continuing the discussion, though.
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